NAND flash memories comprising a NAND cell unit formed by connecting a plurality of EEPROMs in series have been developed. In a NAND flash memory, a plurality of memory cells are simultaneously erased, so as to increase the number of memory cells that are erased in a unit of time, for example. Accordingly, by applying a positive voltage of greater than or equal to 10 V, more specifically, 20 V, for example, to a well region in which a memory cell is formed, electrons are extracted from a charge accumulation layer to a substrate.
During data writing, on the other hand, by keeping the voltage of the well region at 0 V and applying a positive voltage of greater than or equal to 10 V to a source/drain diffusion layer of a memory cell having a charge/discharge capacitance smaller than that of the well region, it is possible to reduce electric power required to charge and discharge the well region, and thereby enhance the operation speed.
Since a positive voltage of 20 V needs to be applied to a control gate electrode of the memory cell, a high-voltage transistor including a gate insulating film greater in thickness than a tunnel insulating film is employed, so as to transfer the voltage to the control gate electrode.
In conventional high-voltage transistors, the concentration of a lightly doped drain (LDD) area differs between a depletion-type (D-type) high-voltage transistor and an enhanced-type (E-type) high-voltage transistor. In this configuration, it is difficult to optimize junction breakdown voltage and surface breakdown voltage in both of the D-type high-voltage transistor and the E-type high-voltage transistor. This causes a problem that reliability of the non-volatile semiconductor memory device decreases due to deterioration in junction breakdown voltage and surface breakdown voltage of the transistors.